About

I'm a digital IC design engineer passionate about pushing the boundaries of computer architecture and AI hardware. My work spans RTL design, verification, and physical implementation of high-performance chips.

China

Background

I started my journey in hardware design during undergrad, where I built my first RISC-V processor on an FPGA. Since then, I've been diving deep into the world of chip design — from RTL coding in Verilog/SystemVerilog to synthesis, place-and-route, and tape-out.

My current research focuses on NPU (Neural Processing Unit) architecture and AI accelerator design. I'm particularly interested in the co-design of algorithms and hardware, exploring how novel compute paradigms can make AI inference more efficient.

When I'm not working on chips, I contribute to open-source hardware projects, write about my learnings, and explore new technologies in the semiconductor space.

Skills & Expertise

Digital Design

RTL Design

Verification

Synthesis

STA

CDC

Low Power

Architecture

Cache Design

Memory Subsystem

NoC

Pipeline

Out-of-Order

Tools & Flow

Vivado

VCS

Verdi

SpyGlass

PrimeTime

Languages

Verilog

SystemVerilog

Chisel

Python

C++

Tcl

Research

NPU Architecture

AI Accelerators

Near-Memory Computing

Chiplet

Education

M.S. in Electrical Engineering

University of Science and Technology · 2023 - 2026

Research focus on NPU architecture and AI chip design.

B.S. in Electronic Engineering

University of Science and Technology · 2019 - 2023

Major in Electronic Science and Technology. GPA: 3.8/4.0.