Blog
Technical articles on digital IC design, computer architecture, FPGA, NPU, and AI chips.
Cache Coherence Protocols: From MSI to MOESI — A Hardware Designer's Perspective
Deep dive into cache coherence protocols for shared-memory multiprocessors. We trace the evolution from simple MSI to complex directory-based MOESI, with RTL implementation considerations.
Designing a Systolic Array for Neural Network Inference: Architecture Deep Dive
A practical guide to designing systolic array accelerators for neural network inference, covering dataflows, memory hierarchy, and PE microarchitecture.
Real-Time FMCW Radar Processing on FPGA: Signal Chain Design and Implementation
End-to-end FPGA implementation of FMCW radar signal processing: 2D FFT, CFAR detection, and angle estimation on Xilinx Zynq. Complete with Verilog RTL examples and MATLAB verification.
Building a RISC-V Out-of-Order Core: Pipeline Design, Branch Prediction, and Memory Ordering
A hands-on guide to designing an out-of-order RISC-V processor core, from the frontend fetch stage through the issue queue to the load-store unit and ROB commit.